Timing Report

Need help reading this report?

Design Name ramcart
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Sun Mar 08 21:15:01 2020
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'XLXN_160.CLKF' has multiple original clock nets 'CART_A6' 'CART_ROM4'.

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for CART_A6
Pad to Pad Delay (tPD) 11.000 ns.
Clock Pad to Output Pad Delay (tCO) 136.400 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
TS1008 0.0 0.0 0 0
TS1009 0.0 0.0 0 0
TS1010 0.0 0.0 0 0
TS1011 0.0 0.0 0 0
TS1012 0.0 0.0 0 0
TS1013 0.0 0.0 0 0
TS1014 0.0 0.0 0 0
TS1015 0.0 0.0 0 0
TS1016 0.0 0.0 0 0
TS1017 0.0 0.0 0 0
AUTO_TS_F2F 0.0 0.0 0 0
AUTO_TS_P2P 0.0 136.4 159 159
AUTO_TS_P2F 0.0 6.2 3 3
AUTO_TS_F2P 0.0 12.7 34 34


Constraint: TS1000

Description: PERIOD:PERIOD_CART_A6:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_CART_ROM4:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_COUNTER2<6>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_COUNTER2<5>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_COUNTER2<4>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_COUNTER2<3>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_COUNTER2<2>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_COUNTER2<1>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1008

Description: PERIOD:PERIOD_COUNTER2<0>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1009

Description: PERIOD:PERIOD_COUNTER1<7>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1010

Description: PERIOD:PERIOD_COUNTER1<6>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1011

Description: PERIOD:PERIOD_COUNTER1<5>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1012

Description: PERIOD:PERIOD_COUNTER1<4>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1013

Description: PERIOD:PERIOD_COUNTER1<3>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1014

Description: PERIOD:PERIOD_COUNTER1<2>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1015

Description: PERIOD:PERIOD_COUNTER1<1>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1016

Description: PERIOD:PERIOD_COUNTER1<0>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1017

Description: PERIOD:PERIOD_CART_ROM3:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CART_ROM3 to RAM_A15 0.000 136.400 -136.400
CART_ROM3 to RAM_A14 0.000 128.500 -128.500
CART_ROM3 to RAM_A13 0.000 120.600 -120.600


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CART_A6 to XLXN_160.CLKF 0.000 6.200 -6.200
CART_ROM3 to COUNTER1<0>.CLKF 0.000 6.200 -6.200
CART_ROM4 to XLXN_160.CLKF 0.000 6.200 -6.200


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
XLXN_160.Q to DTA_LOW_RAM<0> 0.000 12.700 -12.700
XLXN_160.Q to DTA_LOW_RAM<1> 0.000 12.700 -12.700
XLXN_160.Q to DTA_LOW_RAM<2> 0.000 12.700 -12.700



Number of constraints not met: 3

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CART_A6 71.429 Limited by Clock Pulse Width for CART_A6
CART_ROM4 71.429 Limited by Clock Pulse Width for CART_ROM4
COUNTER2<6>.Q 71.429 Limited by Clock Pulse Width for COUNTER2<6>.Q
COUNTER2<5>.Q 71.429 Limited by Clock Pulse Width for COUNTER2<5>.Q
COUNTER2<4>.Q 71.429 Limited by Clock Pulse Width for COUNTER2<4>.Q
COUNTER2<3>.Q 71.429 Limited by Clock Pulse Width for COUNTER2<3>.Q
COUNTER2<2>.Q 71.429 Limited by Clock Pulse Width for COUNTER2<2>.Q
COUNTER2<1>.Q 71.429 Limited by Clock Pulse Width for COUNTER2<1>.Q
COUNTER2<0>.Q 71.429 Limited by Clock Pulse Width for COUNTER2<0>.Q
COUNTER1<7>.Q 71.429 Limited by Clock Pulse Width for COUNTER1<7>.Q
COUNTER1<6>.Q 71.429 Limited by Clock Pulse Width for COUNTER1<6>.Q
COUNTER1<5>.Q 71.429 Limited by Clock Pulse Width for COUNTER1<5>.Q
COUNTER1<4>.Q 71.429 Limited by Clock Pulse Width for COUNTER1<4>.Q
COUNTER1<3>.Q 71.429 Limited by Clock Pulse Width for COUNTER1<3>.Q
COUNTER1<2>.Q 71.429 Limited by Clock Pulse Width for COUNTER1<2>.Q
COUNTER1<1>.Q 71.429 Limited by Clock Pulse Width for COUNTER1<1>.Q
COUNTER1<0>.Q 71.429 Limited by Clock Pulse Width for COUNTER1<0>.Q
CART_ROM3 71.429 Limited by Clock Pulse Width for CART_ROM3

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock CART_A6 to Pad
Destination Pad Clock (edge) to Pad
DTA_LOW_RAM<0> 18.900
DTA_LOW_RAM<1> 18.900
DTA_LOW_RAM<2> 18.900
DTA_LOW_RAM<3> 18.900
DTA_LOW_RAM<4> 18.900
DTA_LOW_RAM<5> 18.900
DTA_LOW_RAM<6> 18.900
DTA_LOW_RAM<7> 18.900
DTA_UP_RAM<0> 18.900
DTA_UP_RAM<1> 18.900
DTA_UP_RAM<2> 18.900
DTA_UP_RAM<3> 18.900
DTA_UP_RAM<4> 18.900
DTA_UP_RAM<5> 18.900
DTA_UP_RAM<6> 18.900
DTA_UP_RAM<7> 18.900
negCE1_RAM_LOWER 17.900
negCE1_RAM_UPPER 17.900

Clock CART_ROM4 to Pad
Destination Pad Clock (edge) to Pad
DTA_LOW_RAM<0> 18.900
DTA_LOW_RAM<1> 18.900
DTA_LOW_RAM<2> 18.900
DTA_LOW_RAM<3> 18.900
DTA_LOW_RAM<4> 18.900
DTA_LOW_RAM<5> 18.900
DTA_LOW_RAM<6> 18.900
DTA_LOW_RAM<7> 18.900
DTA_UP_RAM<0> 18.900
DTA_UP_RAM<1> 18.900
DTA_UP_RAM<2> 18.900
DTA_UP_RAM<3> 18.900
DTA_UP_RAM<4> 18.900
DTA_UP_RAM<5> 18.900
DTA_UP_RAM<6> 18.900
DTA_UP_RAM<7> 18.900
negCE1_RAM_LOWER 17.900
negCE1_RAM_UPPER 17.900

Clock CART_ROM3 to Pad
Destination Pad Clock (edge) to Pad
RAM_A15 136.400
RAM_A14 128.500
RAM_A13 120.600
RAM_A12 112.700
RAM_A11 104.800
RAM_A10 96.900
RAM_A9 89.000
RAM_A8 81.100
RAM_A7 73.200
RAM_A6 65.300
RAM_A5 57.400
RAM_A4 49.500
RAM_A3 41.600
RAM_A2 33.700
RAM_A1 25.800
RAM_A0 17.900


Clock to Setup Times for Clocks


Pad to Pad List

Source Pad Destination Pad Delay
SWITCH CAR_DTA_HIGH<0> 11.000
SWITCH CAR_DTA_HIGH<1> 11.000
SWITCH CAR_DTA_HIGH<2> 11.000
SWITCH CAR_DTA_HIGH<3> 11.000
SWITCH CAR_DTA_HIGH<4> 11.000
SWITCH CAR_DTA_HIGH<5> 11.000
SWITCH CAR_DTA_HIGH<6> 11.000
SWITCH CAR_DTA_HIGH<7> 11.000
SWITCH CAR_DTA_LOW<0> 11.000
SWITCH CAR_DTA_LOW<1> 11.000
SWITCH CAR_DTA_LOW<2> 11.000
SWITCH CAR_DTA_LOW<3> 11.000
SWITCH CAR_DTA_LOW<4> 11.000
SWITCH CAR_DTA_LOW<5> 11.000
SWITCH CAR_DTA_LOW<6> 11.000
SWITCH CAR_DTA_LOW<7> 11.000
SWITCH DTA_LOW_RAM<0> 11.000
SWITCH DTA_LOW_RAM<1> 11.000
SWITCH DTA_LOW_RAM<2> 11.000
SWITCH DTA_LOW_RAM<3> 11.000
SWITCH DTA_LOW_RAM<4> 11.000
SWITCH DTA_LOW_RAM<5> 11.000
SWITCH DTA_LOW_RAM<6> 11.000
SWITCH DTA_LOW_RAM<7> 11.000
SWITCH DTA_UP_RAM<0> 11.000
SWITCH DTA_UP_RAM<1> 11.000
SWITCH DTA_UP_RAM<2> 11.000
SWITCH DTA_UP_RAM<3> 11.000
SWITCH DTA_UP_RAM<4> 11.000
SWITCH DTA_UP_RAM<5> 11.000
SWITCH DTA_UP_RAM<6> 11.000
SWITCH DTA_UP_RAM<7> 11.000
CART_A1 RAM_A0 10.000
CART_A2 RAM_A1 10.000
CART_A3 RAM_A2 10.000
CART_A4 RAM_A3 10.000
CART_A5 RAM_A4 10.000
CART_A6 RAM_A5 10.000
CART_A7 RAM_A6 10.000
CART_ADDR<0> DTA_LOW_RAM<0> 10.000
CART_ADDR<0> DTA_UP_RAM<0> 10.000
CART_ADDR<0> RAM_A7 10.000
CART_ADDR<1> DTA_LOW_RAM<1> 10.000
CART_ADDR<1> DTA_UP_RAM<1> 10.000
CART_ADDR<1> RAM_A8 10.000
CART_ADDR<2> DTA_LOW_RAM<2> 10.000
CART_ADDR<2> DTA_UP_RAM<2> 10.000
CART_ADDR<2> RAM_A9 10.000
CART_ADDR<3> DTA_LOW_RAM<3> 10.000
CART_ADDR<3> DTA_UP_RAM<3> 10.000
CART_ADDR<3> RAM_A10 10.000
CART_ADDR<4> DTA_LOW_RAM<4> 10.000
CART_ADDR<4> DTA_UP_RAM<4> 10.000
CART_ADDR<4> RAM_A11 10.000
CART_ADDR<5> DTA_LOW_RAM<5> 10.000
CART_ADDR<5> DTA_UP_RAM<5> 10.000
CART_ADDR<5> RAM_A12 10.000
CART_ADDR<6> DTA_LOW_RAM<6> 10.000
CART_ADDR<6> DTA_UP_RAM<6> 10.000
CART_ADDR<6> RAM_A13 10.000
CART_ADDR<7> DTA_LOW_RAM<7> 10.000
CART_ADDR<7> DTA_UP_RAM<7> 10.000
CART_ADDR<7> RAM_A14 10.000
CART_ROM3 TRIG_WE_OUT 10.000
CART_ROM3 negCE1_RAM_LOWER 10.000
CART_ROM3 negCE1_RAM_UPPER 10.000
CART_ROM4 RAM_A15 10.000
CART_ROM4 negCE1_RAM_LOWER 10.000
CART_ROM4 negCE1_RAM_UPPER 10.000
DTA_LOW_RAM<0> CAR_DTA_LOW<0> 10.000
DTA_LOW_RAM<1> CAR_DTA_LOW<1> 10.000
DTA_LOW_RAM<2> CAR_DTA_LOW<2> 10.000
DTA_LOW_RAM<3> CAR_DTA_LOW<3> 10.000
DTA_LOW_RAM<4> CAR_DTA_LOW<4> 10.000
DTA_LOW_RAM<5> CAR_DTA_LOW<5> 10.000
DTA_LOW_RAM<6> CAR_DTA_LOW<6> 10.000
DTA_LOW_RAM<7> CAR_DTA_LOW<7> 10.000
DTA_UP_RAM<0> CAR_DTA_HIGH<0> 10.000
DTA_UP_RAM<1> CAR_DTA_HIGH<1> 10.000
DTA_UP_RAM<2> CAR_DTA_HIGH<2> 10.000
DTA_UP_RAM<3> CAR_DTA_HIGH<3> 10.000
DTA_UP_RAM<4> CAR_DTA_HIGH<4> 10.000
DTA_UP_RAM<5> CAR_DTA_HIGH<5> 10.000
DTA_UP_RAM<6> CAR_DTA_HIGH<6> 10.000
DTA_UP_RAM<7> CAR_DTA_HIGH<7> 10.000
LDS OE_RAM_LOWER 10.000
SWITCH OE_RAM_LOWER 10.000
SWITCH OE_RAM_UPPER 10.000
SWITCH RAM_A0 10.000
SWITCH RAM_A1 10.000
SWITCH RAM_A10 10.000
SWITCH RAM_A11 10.000
SWITCH RAM_A12 10.000
SWITCH RAM_A13 10.000
SWITCH RAM_A14 10.000
SWITCH RAM_A15 10.000
SWITCH RAM_A2 10.000
SWITCH RAM_A3 10.000
SWITCH RAM_A4 10.000
SWITCH RAM_A5 10.000
SWITCH RAM_A6 10.000
SWITCH RAM_A7 10.000
SWITCH RAM_A8 10.000
SWITCH RAM_A9 10.000
SWITCH negCE1_RAM_LOWER 10.000
SWITCH negCE1_RAM_UPPER 10.000
UDS OE_RAM_UPPER 10.000



Number of paths analyzed: 196
Number of Timing errors: 196
Analysis Completed: Sun Mar 08 21:15:01 2020